Jiahua Huang 黄嘉华

Email: jiah.huang@foxmail.com

Research Interest

My expertise lies in Machine Learning Systems (MLSys) and resource management, with a specialized focus on enhancing Large Language Model inference through innovative AI methodologies.

I am actively seeking an internship in LLM inference optimization. Please feel free to reach out if you have or know of any suitable opportunities. I’m always open to connecting with professionals in the field.

Education

South China University of Technology, Guangzhou, China

• Ph.D. in Computer Science, advised by Prof. Weiwei Ling, Sep. 2023 – Present

Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China

• Master of Engineering, Electronic Information, advised by Prof. Yang Wang, Sep. 2020 – Jun. 2023

Jiangnan University, Wuxi, China

• Bachelor of Engineering, Digital Media Technology, Sep. 2015 – Jun. 2019

Publications

• [AAAI '26] Experiential Fairness: Bridging the Gap between User Experience and Resource-Centric Fairness in Online LLM Services [paper] [poster] [code]
  • Jiahua Huang, Wentai Wu, Yongheng Liu, Guozhi Liu, Yang Wang, Weiwei Lin
  • The 40th Annual AAAI Conference on Artificial Intelligence (CCF-A), Accepted on 08 Nov 2025.
• [CSUR '25] On Efficiency, Fairness and Security in AI Accelerator Resource Sharing: A Survey [paper] [url]
  • Jiahua Huang, Weiwei Lin*, Wentai Wu, Yang Wang, Haocheng Zhong, Xinhua Wang, Keqin Li
  • ACM Computing Surveys (SCI Q1 Top, IF 23.8), Accepted on 24 Feb 2025.

Project

• EcoMoE — SLO-aware energy optimization for offloaded MoE inference (HPCA ‘27 submission)
  • We identify a thick memory-access wall in MoE decode by combining SM_ACTIVE vs. NVML utilization mismatch, load ramps, cache sweeps, and byte-level HBM/PCIe accounting, showing that the bottleneck comes from the expert-weight access path rather than low load.
  • Locked-clock sweeps then show why this wall is useful for DVFS: MoE decode has a broad latency-flat region, while dense LLM decode is much more clock-sensitive and therefore offers far less safe downclocking headroom.

• PACE — KV-working-set-aware GPU DVFS for LLM serving (ATC ‘26 submission)
  • We show that decode-time energy in continuous batching tracks the active KV working set, exposing memory pressure that active batch size alone cannot describe.
  • Based on this signal, PACE is a lightweight feedforward controller that uses only runtime scheduler state to reduce decode energy while preserving tail-latency SLOs.

• ExFairS
  • ExFairS is a scheduling framework for online LLM services that bridges the gap between system-centric fairness metrics and actual user experience.
  • It introduces an SLO-aware fairness score and combines credit exchange with a priority queue to improve user-perceived service quality.

Experiences

Alibaba Group, Hangzhou

• Research Intern, Oct. 2021 – Oct. 2022

Alibaba Cloud, Hangzhou

• Research Intern, Aug. 2021 – Sep. 2021

CCB Fintech, Shenzhen

• Software Engineer, Jul. 2019 – Jun. 2020

Awards and Fellowships

[Siat Digital Institute Outstanding Student of the Year Award]

• Siat Digital Institute, 2022